Signal Integrity(SI)
WHY Signal Integrity (SI) Simulation?
- At low-speed signal interface, we seldom experience any major problems with signal quality. Nowadays, as signal speed increases and the design of chips, packages, passive components become more complex as well, you may experience reflections, distortions, delays, crosstalk, and impedance mismatch, which can seriously damage the signal transmission, signal integrity (SI) is increasingly important aspect of successful system design.
WHAT Benefits of Signal Integrity (SI) Simulation?
- The electrical product design cycle becomes shorter and shorter as the AI, Machine learning, 5G, Automotive, IoT rapid development, accelerate Time to Market (TTM) of the product is the key point in today's competitive world. SI analysis helps to identify the potential high speed signal problems in the early design phase and find out the suitable high speed layout rule to avoid unexpected failure before fabrication and testing.
WHEN Do You Need Signal Integrity (SI) Analysis?
There are two types of signal integrity (SI) analysis that can be considered at project design stages. :
Our SI Simulation Service & Experience:
Pre-Simulation
- Stack up material and layer structure selection
- High speed topology type exploration and system budget evaluation
- High speed component floor-planning and routing length evaluation
- High speed trace/via impedance matching and fan-out footprint pattern optimization
- I/O buffer driver and termination scheme strategy combination Derive layout guideline for specific high-speed interface
Q&A
The following data need to be prepared ahead of the simulation project starting:
Stackup:
- Provide information about the PCB stackup, including the number of layers, material types for each layer, and thickness.
Package Model:
- Information about the electrical characteristics of the IC package. This includes details about parasitic components within the package, such as capacitance, inductance, and resistance.
Connector Model:
- If the system includes connectors, please provide the S-parameter models for the connectors. This helps ensure the performance of connectors in high-speed data transmission.
Chip and Device IBIS/IBIS-AMI/DLL Models:
- If IBIS (Input/Output Buffer Information Specification/Non-SerDes), IBIS-AMI (Algorithmic Model Interface/SerDes) models, and DLL (Dynamic Link Library) models are used, it is necessary to provide the corresponding files, that describe the input/output buffer behavior of chips and devices, it enables to provide the most optimized eye diagrams and equalization capability for simulation analysis.
Design Guide:
- Provide any relevant design guides or referenced documents that we can offer best suggestions tailored to the specific simulation project.
2. Can simulation analysis be performed only on the longest trace of the configuration design?
Yes, typically SI simulations adopt the worst-case scenario for evaluation. However, it is suggested to include the shortest trace in the analysis as well because the longest and shortest traces represent the worst cases for loss (IL) and reflection (RL). Analyzing both the longest and shortest traces provides a more comprehensive and accurate signal quality analysis, enhancing production yield.
3. How is simulation analysis executed, and approximately how long does it take for a single run?
Generally, whether it's pre-sim or post-sim analysis, the results will provide suggestions for optimizing the configuration design. Customers can make modifications based on these suggestions, and it can be provided for the second run afterward. Each topology typically takes around 7 weekdays.
4. How is the pricing calculated?
Pricing is determined based on the size of the system (block diagram). For further details, please contact HERE.